Semiconductor memory devices typically include a number of buffers, including input data buffers and address buffers. Also, such memory devices generally operate in at least two modes, including a normal or functional mode in which data is written to or read from memory cells in a memory array of the device, and a power-down mode, in which most of the memory circuitry is disabled or otherwise inactive.
In conventional practice, input data buffers and address buffers of a given memory device can draw significant current even when the given device is in a power-down mode. This is because such buffers are typically coupled to external data and address buses that remain active within a higher-level memory system even when the given memory device is in the power-down mode, and activity on the external data and address buses results in dynamic current being drawn by the input data buffers and address buffers.
Previous attempts to alleviate this problem have utilized combinational logic gates and an additional control signal to disable the input data buffers and address buffers when the memory device that includes those buffers enters a power-down mode. Unfortunately, this approach is deficient in that it unduly impacts the performance of the buffers when the device is in the functional mode. For example, buffers configured in this manner may require longer setup times, thereby reducing the speed at which the buffers can operate. Moreover, implementation of the combinational logic gates utilized in this approach generally requires a large number of transistors, which significantly increases the circuit area of the device. Finally, the control signal usually must be applied to logic gates associated with a large number of different buffers, and thus must be generated in a manner that allows it to drive heavy loads. A control signal of this type can be difficult to generate, requiring drive circuitry that consumes significant current and occupies a large amount of circuit area.
It is therefore apparent that a need exists for an improved approach to reducing dynamic current consumption by input data buffers and address buffers when a memory device is in its power-down mode, without negatively impacting the performance of these buffers when the device is in its functional mode.